Objective The time delay integration (TDI) CMOS image sensor improves the signal-to-noise ratio (SNR) by accumulating the same image signal over multiple exposures, making it widely applicable in high-SNR-demanding fields such as aerospace, satellite imaging, and semiconductor testing. To further enhance the circuit's SNR, the number of accumulation levels in the analog domain accumulators is increased. However, parasitic capacitance and circuit noise also increase with the higher accumulation stages, which limits the improvement of SNR. Traditional analog accumulators can no longer meet the requirements of such applications. To reduce the impact of parasitic effects on accumulation accuracy, a compensation method utilizing polarity inversion switches and adaptive positive feedback capacitors is introduced. Furthermore, in response to the core technical bottleneck caused by front-end circuit noise, which limits SNR enhancement in high-stage analog accumulators, an innovative architecture for the TDI CMOS image sensor's analog domain accumulator based on fully parallel correlated multi-sampling (CMS) technology is proposed.

Methods CMS technology is integrated with the analog domain accumulator using shared capacitors, resulting in a fully parallel CMS-based architecture for the analog domain accumulator (Fig.4) and its circuit timing sequence (Fig.5). This architecture allows the input signal to be sampled and averaged multiple times while enabling signal transfer and accumulation based on its structural characteristics, without the need for additional buffers. The architecture is designed to effectively suppress circuit noise within a more compact chip area, while ensuring that the TDI accumulation line rate remains unaffected, thereby enhancing the SNR performance of the TDI CMOS image sensor analog domain accumulator. By abstracting the mathematical model of CMS technology (Fig.2) and deeply coupling it with the TDI SNR model, the circuit's SNR enhancement is optimized, and a systematic performance evaluation is conducted.

Results and Discussions To evaluate the SNR improvement of the proposed architecture after its actual design, an analog domain accumulator based on fully parallel CMS technology was implemented in a 2048×128 TDI CMOS image sensor using a 55 nm CMOS process. Simulations comparing the ideal (Fig.9) and actual (Fig.10) SNR improvements show that the actual SNR improvement closely matches the ideal values, demonstrating a significant enhancement in the circuit’s SNR. Simulation of the circuit's effective accumulation order (Fig.11) reveals that the proposed circuit achieves a 128-order accumulation effect, equivalent to the 625.461-order effective accumulation result of the circuit in 10, significantly enhancing the circuit's effective accumulation order. The circuit's quality factor calculation indicates that it performs excellently in terms of power consumption, SNR, and line frequency (Tab.1). Additionally, image processing tests confirm that the circuit effectively suppresses low-frequency noise from the front-end circuit, leading to a noticeable improvement in SNR. This results in fewer imaging noise spots and clearer image quality.

Conclusions An analog domain accumulator architecture based on fully parallel correlated multi-sampling technology is designed, utilizing shared capacitors to synchronize correlated multi-sampling and analog accumulation. This approach effectively suppresses circuit noise while maintaining the TDI accumulator's line frequency, achieving a significant improvement in circuit SNR and enabling a higher effective accumulation stage with a more compact chip area. The proposed method, implemented using a 55 nm standard CMOS process, is successfully applied in a 2048-column, 128-stage TDI image sensor. Post-layout simulation results show that, at a line frequency of 10.85 kHz, the SNR of the 128-stage accumulation improves by 27.962 dB. Of this, the polarity inversion switch and adaptive positive feedback capacitor method contribute 20.9 dB, while the CMS technology provides an additional 7.062 dB. The power consumption per column is 301 µW, with an area of 0.361 mm² for the 128-stage accumulator per column. The CMS circuit reduces the area by more than 40% compared to traditional designs, reducing the area of each column of the proposed accumulator to 98.5%. The circuit effectively reduces noise and enhances the SNR, significantly improving imaging accuracy under low-light conditions.